1. Field of the Invention
The present invention relates to digital memory devices and operation thereof, and more particularly to NAND flash memory having internal ECC processing and methods of operation thereof.
2. Description of Related Art
NAND flash memory is popular for data storage. The cost versus density advantage of single level cell (“SLC”) NAND flash memory in densities of 512 Megabits and higher is largely due to the inherently smaller memory cell size used in SLC NAND flash technology.
NAND flash memory is also becoming popular for a variety of applications in addition to data storage, including code shadowing. Although commonly used SLC NAND flash memory has architectural, performance, data integrity, and bad block limitations that make it difficult to support the high speed code shadow applications for which serial NOR flash memory is well suited, various techniques have been developed to adapt NAND flash memory to such applications.
Error Correction Code (“EEC”) algorithms have been developed to manage the data integrity issue. In one approach, an internal ECC calculation is done during page programming, and the resulting EEC information is stored in the extra 64-Byte area known as the spare area for each page. During the data read operation, the ECC engine verifies the data according to the previously-stored ECC information, and to a limited extent, makes the indicated corrections. The verification and correction status is indicated by ECC Status Bits ECC-1 and ECC-0, in the following manner. ECC-1, ECC-0 status (0:0) indicates that the entire data output is successful, without the need for any ECC correction. ECC-1, ECC-0 status (0:1) indicates that the entire data output is successful, with 1˜4 bit/page ECC corrections in either a single page or multiple pages. ECC-1, ECC-0 status (1:0) indicates that the entire data output contains more than 4 bits errors only in a single page which cannot be repaired by ECC. The data is not suitable for use. In the Continuous Read Mode, an additional command may be used to read out the Page Address (PA) of the page containing the errors. ECC-1, ECC-0 status (1:1) indicates that the entire data output contains more than 4 bits errors/page in multiple pages. In the Continuous Read Mode, the additional command provides the Page Address (PA) of the last page containing the errors. The PAs of the other failed pages is not reported.